The disclosed embodiments of the present invention relate to wireless communication, and more particularly, to a wireless communication receiver (e.g., a digital television receiver), a wireless communication receiving method and a television receiver capable of sharing a data storage module (e.g., a memory) between a deinterleaver and a signal processing circuit (e.g., an MPEG decoder, an H.264 decoder or an AVS decoder).
Recently, the orthogonal frequency division multiplexing (OFDM) technique is widely adopted in a variety of wireless communication systems, such as digital television systems. In general, the digital television system is a television system which uses digital signals instead of commonly used analog signals for delivering television program contents. That is, the digital television system performs signal processing operations, such as digitization, compression, etc, upon an original signal including video information and audio information, and accordingly generates data streams. Next, the generated data streams are broadcasted via wireless communication means. Regarding a user end, a digital television receiver is used for receiving a wireless communication signal and extracting a video signal and an audio signal from the received wireless communication signal through adequate signal processing operations, such as the demodulating operation, the deinterleaving operation, the decoding operation, etc. Program contents of a channel selected by the user are played via output devices (e.g., a television screen and a speaker).
The digital television standards presently used in different areas in the world may be different. For example, People's Republic of China (P.R.C.) has defined its own digital television standard. However, no matter which digital television standard is employed, any digital television signal should be received by a digital television receiver. Please refer to FIG. 1, which is a block diagram illustrating a conventional digital television receiver 100. The digital television receiver 100 includes an antenna 102, a tuner 104, a demodulator 106, a backend decoder 108, and a plurality of memories 110 and 112. The antenna 102 receives the digital television signal which is a radio frequency signal. Next, the tuner 104 performs down-conversion and channel selection upon the received digital television signal, and the demodulator 106 performs demodulation upon an output of the tuner 104 for extracting a bit stream transmitted by the digital television signal. The backend decoder 108 generates video/audio signals to the following output devices (e.g., a television screen and a speaker) by performing a decoding operation, such as an MPEG (Moving Picture Experts Group) decoding operation, an H.264 decoding operation or an AVS (Audio Video coding Standard) decoding operation, upon the bit stream generated from the demodulator 106. In this way, program contents of a channel selected by the user are played on the output devices. In general, the backend decoder 108 and the demodulator 106 are designed separately, and are therefore disposed in different chips. Thus, the demodulator 106 has its own dedicated memory 110; similarly, the backend decoder 108 has its own dedicated memory 112.
Generally speaking, an interleaving operation may be performed to arrange the original data in a non-contiguous way before a transmitting end transmits the wireless communication signal, thereby mitigating the effect caused by channel fading. Regarding the digital television signal broadcasting, when the transmitting end is equipped with an interleaver, the digital television receiver 100 at the receiving end is therefore required to have a corresponding deinterleaver. For example, taking the digital television standard defined by P.R.C. for example, a convolutional deinterleaving operation is employed to arrange the original data in a non-contiguous way. However, compared with the interleaving techniques defined in other digital television standard (e.g., the DVB-T standard), the convolutional deinterleaver complying with the digital television standard defined by P.R.C. requires a large data buffer amount due to the shift registers implemented in a plurality of interleaving branches. This also means that the deinterleaving circuit in the demodulator 106 needs a large storage space to accomplish the deinterleaving operation. Thus, the conventional design often uses chip's external memory (e.g., the memory 110) to provide the desired storage space. However, as the memory 110 is only accessible to the demodulator 106 (for example, the memory 110 is only accessible to the deinterleaving circuit within the demodulator 106) and the memory 112 is only accessible to the backend decoder 108, such a conventional hardware configuration lacks flexibility in the use of memories. Besides, the production cost cannot be effectively reduced due to these dedicated memories 110 and 112.